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Professor
Peilin Liu

 

Peilin Liu ,  Professor
Microelectronics Building 3-309
Shanghai JiaoTong University
800 Dongchuan Road, Shanghai 200240, China
Tel: +86 21 3420 6182
Email: liupeilin@sjtu.edu.cn
Biography
      Peilin Liu is a PhD, Graduated from the University of Tokyo majoring in Electronic Engineering in 1998 and worked there as a Research Fellow  in 1999. From 1999 to 2003 she worked  as a Senior Researcher for Central Research Institute of Fujitsu, Tokyo. Her research mainly focuses on Signal processing, low power computing architecture,Application-orientedSoC design and Verification. She is now a professor of Department of Electronic Engineering in Shanghai Jiao Tong University,executive director  ofShanghai Key Laboratory of Navigation and Location Based Service and responsible for a series of important projects, such as BDSSoC Platform Development, Low power and High-Performance communication DSP.Dr. Liu  is the chair of Shanghai chapter of  IEEE Circuit and System. She has published 50 journal articlesand has more than 50 awarded patents. She is the author of "MIPS Architecture and Programming ," 2008.
Research Areas
  • 1. Computer Architecture
  • 2. DSP and SoC for GNSS and Multimedia
  • 3. multimedia signal processing

Shanghai Key Laboratory of Navigation and Location Based Service: http://nls.sjtu.edu.cn/

 

MediaSoC Lab: http://mediasoc.sjtu.edu.cn

 
Selected Publications
  • 1. Ji Kong; Peilin Liu; Yu Zhang; "Atomic Streaming: A Framework of On-Chip Data Supply System for Task Parallel MPSoCs", in 2011 IEEE Computer Architecture Letters
  • 2. Ji Kong; Peilin Liu; Xianmin Chen; Jin Wang; Xingguang Pan; Jun Wang; He Xiao; Zhenqi Wei; Rendong Ying; “Next-generation consumer audio application specific embedded processor”, in 2010 IEEE 8th Symposium on Application Specific Processors (SASP)
  • 3. J. Wang, P. Liu, J. Kong, and R. Ying. Split Table Extension: A Low Complexity LVQ Extension Scheme in Low Bitrate Audio Coding. Signal Processing Letters, IEEE, 17(1):59--62, 2010.
  • 4. X. Chen, P. Liu, D. Zhou, J. Zhu, X. Pan, and S. Goto. A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder. IEICE Transactions on Electronics,93(3):253--260, 2010.
  • 5. X. Chen, P. Liu, J. Zhu, D. Zhou, and S. Goto. Block-pipelining cache for motion compensation in high definition H. 264/AVC video decoder. In Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pages 1069--1072. IEEE, 2009
  • 6. J. Kong and P. Liu. A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC. In VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP, pages 402--407. IEEE.
Books and Patents
  • 1. “MIPS Architecture and Programming ,"  2008, Science and Technology Publishing House
Courses
  • 1. EI205: “Digital Circuit,” Spring

 

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