Mengwei Si

Address:上海市闵行区东川路800号上海交通大学闵行校区电信群楼1-501

Phone:

Email:mengwei.si@sjtu.edu.cn

Research Center:INDEPENDENT LABORATORY

Personal Home Page:simengwei.com.cn

Biography
Dr. Mengwei received his B.S. degree in Electronic Engineering from Shanghai Jiao Tong University, Shanghai, China, in 2012. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University, West Lafayette, USA, in 2018. Before joining Shanghai Jiao Tong University in 2021, he was a postdoc with Department of Electrical and Computer Engineering at Purdue University. He is currently an associate professor with Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, China. His research interests include semiconductor fabrication, semiconductor materials and devices, ferroelectric materials, nanoscale devices and technology and atomic layer deposition. He s published over 100 papers in international journals and conferences, including 4 ESI highly cited papers, with over 2000 citations in recent 5 years. He has published research papers as first author on Nature Electronics and Nature Nanotechnology. He has published research papers as first author on Nature Electronics and Nature Nanotechnology. He has published 12 papers on IEDM and 7 papers on VLSI, which are the premier conference in microelectonic devices. His work was reported by well-recognized media for over 20 times. He gave over 20 invited and contributed talks in international conferences.
ResearchDirection
CMOS integrated circuits, semiconductor devices, ferroelectric materials and devices, oxide semiconductors, nanoscale devices, energy efficient devices, III-V/Ge high mobility semiconductors, atomic layer deposition.
Books and Patent

  • M. Si, X. Li, W. Wu, S. Alghamdi, and P. D.Ye, “Low-Frequency Noise in III–V, Ge, and 2D Transistors,” In Noise in Nanoscale Semiconductor Devices. Cham, Switzerland: Springer, 2020, ch. 10, pp. 335-357.
  • H. Zhou, J. Noh, H. Bae, M. Si, and P. D.Ye, “Field-Effect Transistors 4,” In Gallium Oxide. Cham, Switzerland: Springer, 2020, ch. 34, pp. 623-638.

Selected Publications

  • M. Si, Z. Lin, Z. Chen, and P. D. Ye, “First Demonstration of Atomic-Layer-Deposited BEOL-Compatible In2O3 3D Fin Transistors and Integrated Circuits: High Mobility of 113 cm2/V⋅s, Maximum Drain Current of 2.5 mA/μm and Maximum Voltage Gain of 38 V/V in In2O3 Inverter,” in 2021 IEEE Symposium on VLSI Technology (VLSI), 2021.
  • M. Si, Z. Z, S.-C. Chang, N. Haratipour, D. Zheng, J. Li, U. E. Avci, and P. D. Ye, “Asymmetric Metal/α-In2Se3/Si Crossbar Ferroelectric Semiconductor Junction,” ACS Nano, vol. 15, no. 3, pp. 5689-5695, 2021.
  • M. Si, A. Charnas, Z. Lin, and P. D. Ye, “Enhancement-Mode Atomic-Layer-Deposited In2O3 Transistors with Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing and Stability in Hydrogen Environment,” IEEE Trans. Electron Devices, vol. 68, no. 3, pp.1075-1080, 2021.
  • M. Si, Y. Hu, Z. Lin, X. Sun, A. Charnas, D. Zheng, X. Lyu, H. Wang, K. Cho, and P. D. Ye, “Why In2O3 Can Make 0.7 nm Atomic Layer Thin Transistors?,” Nano Lett., vol. 21, no. 1, pp. 500-506, 2021.
  • M. Si, Z. Lin, A. Charnas, and P. D. Ye, “Scaled Atomic-Layer-Deposited Indium Oxide Nanometer Transistors with Maximum Drain Current Exceeding 2 A/mm at Drain Voltage of 0.7 V,” IEEE Electron Device Lett., vol. 42, no. 2, pp. 184-187, 2021. (Editor’s Pick)
  • M. Si, J. Andler, X. Lyu, C. Niu, S. Datta, R. Agrawal, and P. D. Ye, “Indium-Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating,” ACS Nano, vol. 14, no. 8, pp. 11542-11547, 2020.
  • M. Si, Y. Luo, W. Chung, H. Bae, D. Zheng, J. Li, J. Qin, G. Qiu, S. Yu, and P. D. Ye, “A Novel Scalable Energy-Efficient Synaptic Device: Crossbar Ferroelectric Semiconductor Junction,” in 2019 IEEE International Electron Devices Meeting (IEDM), 2019, pp. 130-133.
  • M. Si, A. K. Saha, S. Gao, G. Qiu, J. Qin, Y. Duan, J. Jian, H. Wang, W. Wu, S. K. Gupta, and P. D. Ye, “A Ferroelectric Semiconductor Field-Effect Transistor,” Nat. Electron., vol. 2, pp. 580-586, 2019.
  • M. Si, X. Lyu, P. Shrestha, X. Sun, H. Wang, K. P. Cheung, and P. D. Ye, “Ultrafast Measurements of Polarization Switching Dynamics on Ferroelectric and Anti-Ferroelectric Hafnium Zirconium Oxide,” Appl. Phys. Lett., vol. 115, p. 072107, 2019.
  • M. Si, X. Lyu, and P. D. Ye, “On the Ferroelectric Polarization Switching of Hafnium Zirconium Oxide in Ferroelectric/Dielectric Stack,” ACS Appl. Electron. Mater., vol. 1, no. 5, pp. 745-751, 2019.
  • M. Si†, P.-Y. Liao†, G. Qiu, Y. Duan, and P. D. Ye, “Ferroelectric Field-effect Transistors Based on MoS2 and CuInP2S6 Two-dimensional Van der Waals Heterostructure,” ACS Nano, vol. 12, no. 7, pp. 6700-6705, 2018.
  • M. Si, C.-J. Su, C. Jiang, N. J. Conrad, H. Zhou, K. Mazie, G. Qiu, C.-T. Wu, A. Shakouri, M. A. Alam, and P. D. Ye, “Steep Slope Hysteresis-free Negative Capacitance MoS2 Transistors,” Nat. Nanotechnol., vol. 13, pp. 24-28, 2018.
  • M. Si, C. Jiang, C.-J. Su, Y.-T. Tang, L. Yang, W. Chung, M. A. Alam and P. D. Ye, “Sub-60 mV/dec Ferroelectric HZO MoS2 Negative Capacitance Field-effect Transistor with Internal Metal Gate: the Role of Parasitic Capacitance,” in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 573-576.
  • M. Si, N. J. Conrad, S. Shin, J. Gu, J. Zhang, M. A. Alam, and P. D. Ye, “Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs,” IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3508-3515, 2015.
  • M. Si, J. J. Gu, X. Wang, J. Shao, X. Li, M. J. Manfra, R. G. Gordon, and P. D. Ye, “Effects of forming gas anneal on ultrathin InGaAs nanowire metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 102, no. 9, p. 93505, 2013.