上海交通大学电子工程系

赵昕副教授

地址：上海市东川路800号电院1号楼543

电话：16601848872

邮箱：xinzhao@sjtu.edu.cn

研究中心：微波与射频技术研究中心

个人主页：http://xinzhao.sjtu.edu.cn/

个人简介

赵昕，上海交通大学长聘教轨副教授，博士生导师。赵昕本科与博士分别毕业于北京大学和麻省理工学院，主要研究方向为半导体在人工智能与分子生物中的应用，注重工程研究的产业转化。

研究领域

As transistor size is approaching atomic limit, Moore’s law will come to an inevitable end. The next era of semiconductor innovation will be interdisciplinary. We seek to leverage semiconductor technology to tackle some of the toughest challenges in biology and artificial intelligence. We focus on the following research areas:

AI training accelerator based on novel semiconductor devices
3D integrated chips for ultra high throughput DNA synthesis and sequencing

研究方向

Novel semiconductor device, circuits and systems for molecular biology and AI.

获奖情况

《麻省理工科技评论》亚太区“35岁以下科技创新35人” （2022）

苏州市姑苏领军人才（2022）

苏州市工业园区金鸡湖领军人才计划（2020）

国家级青年人才计划（2018）

科研项目

(1) 国家级青年人才计划, 2021-01至2024-01, 300万元, 在研, 主持
(2) 美国国立卫生研究院 (NIH), Small Business Innovation Research, Miniaturized Global Coagulation Assay System in Neonatal and Pediatric Settings, 1R43HL140686-01, 2018-02至2019-09, 15万美元, 结题, 主持
(3) 美国自然科学基金 (NSF), Small Business Innovation Research, A novel shear-based platelet function test (PFT) using 3D MEMS electrodes, 1722200, 2017-07至2018-12, 22.5万美元, 结题, 主持
(4) Semiconductor Research Corporation, III-V Vertical Nanowire MOSFETs with Band Engineering in the Transport Direction, 2017-01至2019-12, 30万美元, 结题, 参与
(5) Lam Research, Multigate III-V MOSFETs, 2014-01至2018-12, 32万美元, 结题, 参与
(6) 美国自然科学基金 (NSF), Superlattice-Source Nanowire FET with Steep Subthreshold Characteristics, 2010-09至2020-08, 140万美元, 结题, 参与

重要论文

Journal PUblications (Chronological order)

1. X. Zhao, A. Vardy, J. A. del Alamo, “Fin-Width Scaling of Highly-doped InGaAs Fins”, IEEE Transactions of Electron Devices, vol. 66, no. 6, pp. 2563-2568, May. 2019.

2. X. Zhao, A. Vardy, and J. A. del Alamo, “Excess OFF-State Current in InGaAs FinFETs: Physics of the Parasitic Bipolar Effect”, IEEE Transactions of Electron Devices, vol. 66, no. 5, pp. 2113-2118, Mar. 2019.

3. X. Zhao, C. Heidelberger, E. A. Fitzgerald, W. Lu, A. Vardy, and J. A. del Alamo, “Sub-10 nm Diameter InGaAs Vertical Nanowire MOSFETs: Ni vs. Mo contacts”, IEEE Transactions of Electron Devices, vol. 65, no. 9, pp. 3762-3768, Sep. 2018.

4. X. Zhao, W. Lu, A. Vardi and J. A. del Alamo, “Shrinking the Vertical Nanowire MOSFET”, Compound Semiconductor Magazine, vol. 24, no. 4, pp. 52-57, June. 2018.

5. X. Zhao, A. Vardy, and J. A. del Alamo, “Excess Off-State Current in InGaAs FinFETs”, IEEE Electron Device Letters, vol. 39, no. 4, pp.476-479, April. 2018.

6. A. Vardi, J. Lin, W. Lu, X. Zhao, A. Fernando-Saavedra, and J. A. del Alamo, “A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs,” IEEE Transactions on Semiconductor Engineering, vol. 30, no. 4, pp. 468-474.

7. X. Zhao, A. Vardy, J. A. del Alamo, “Sub-thermal Subthreshold Characteristics in Top-down InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs”, IEEE Electron Device Letters, vol. 38, no. 7, pp.855-858, July. 2017.

8. X. Zhao, C. Heidelberger, E. A. Fitzgerald and J. A. del Alamo, “Source/Drain Asymmetry in InGaAs Vertical Nanowire MOSFETs”, IEEE Transactions of Electron Devices, vol. 64, no. 5, pp. 2161-2165, May 2017.

9. W. Lu, X. Zhao, D. Choi, S. E. Kazzi, J. A. del Alamo, “Alcohol-Based Digital Etch for III–V Vertical Nanowires With Sub-10 nm Diameter”, IEEE Electron Device Letters. vol. 38, no. 5, pp.548-551, May. 2017.

10. J. A. del Alamo, A. Vardi and X. Zhao, “InGaAs finFETs for Future CMOS”, Compound Semiconductor Magzine, vol. 22, no. 6, pp. 19-25, Aug. 2017.

11. J. A. del Alamo, D. A. Antoniadis, J. Lin, W. Lu, A. Vardi and X. Zhao, “Nanometer-Scale III-V MOSFETs,” IEEE Journal of the Electron Devices Society, vol. 4, no. 5, pp. 205-214, Jul. 2016.

12. H. Chong, X. Jia, L. Wei, S-C. Tan, X. Zhao, J. Joannopoulos, and Y. Fink, “Crystalline Silicon Core Fibres from Aluminum Core Performs”, Nature Communication, vol. 6, Feb.2015.

13. A. Vardi, W. Lu, X. Zhao, J. A. del Alamo, “Nano-scale Mo Ohmic Contacts to III-V Fins”, IEEE Electron Device Letters. vol. 36, no. 2, pp.126-128, Feb. 2015.

14. X. Zhao, J. A. del Alamo, “Nanometer-Scale Vertical-Sidewall Reactive Ion Etching of InGaAs for 3-D III-V MOSFETs”, IEEE Electron Device Letters, vol. 35, no. 5, pp. 521-523, May. 2014.

15. J. Lin, X. Zhao, D. A. Antoniadis, and J. A. del Alamo, “A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs”, IEEE Electron Device Letters, vol. 35, no. 4, pp. 440-442, Apr. 2014.

16. S. Xu, Y. Yang, D. Pei, X. Zhao, Y. Wnag, W. Sun, B. Ma, Y. Li, S. Xie, L.-M. Peng, “A Waveguide-Like Effect Observed in Multiwalled Carbon Nanotube Bundles,” Advanced Functional Materials, vol. 20, no. 14, pp. 2263-2268, Jun. 2010.

Conference Proceedings (Chronological order)

1. J. A. del Alamo, X. Cai, W. Lu, A. Vardi and X. Zhao, “III-V CMOS: Quo Vadis?” Invited Talk at Compound Semiconductor Week, Cambridge, US, May 29 – June 1, 2018.

2. J. A. del Alamo, X. Cai, W. Lu, A. Vardi and X. Zhao, “III-V CMOS: Quo Vadis?” Invited Talk at Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2018), Granada, Spain, March 19-21, 2018.

3. X. Zhao, C. Heidelberger, E. A. Fitzgerald W. Lu, A. Vardi and J. A. del Alamo, “Sub-10 nm InGaAs Vertical Nanowire MOSFETs”, in IEDM Tech. Dig., 2017, pp. 413-416.

4. A. Vardi, L. Kong, W. Lu, X. Cai, X. Zhao, J. Grajal and J. A. del Alamo, “Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation”, in IEDM Tech. Dig., 2017, pp. 429-432.

5. J. A. del Alamo, X. Zhao, W. Lu, and A. Vardi, “Towards Sub-10 nm Diameter InGaAs Vertical Nanowire MOSFETs and TFETs.” Invited Talk at 2017 5th Berkeley Symposium on Energy Efficient Electronic Systems,, Berkeley, CA, October 19-20, 2017.

6. J. A. del Alamo, X. Cai, J. Lin, W. Lu, A. Vardi, and X. Zhao, “CMOS Beyond Si: Nanometer-Scale III-V MOSFETs” Invited Talk at 31st Annual IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Miami, FL, October 19-21, 2017, pp. 25-29.

7. X. Zhao, C. Heidelberger, E. A. Fitzgerald and J. A. del Alamo, “Top-down InGaAs Vertical Nanowire MOSFETs with Record Characteristics”, Compound Semiconductor Week, Berlin, Germany, May 14-18, 2017.

8. A. Vardi, J. Lin, W. Lin, X. Zhao, J. A. del Alamo “High Aspect Ratio InGaAs FinFETs with Sub-20 nm Fin Width,” in VLSI Tech. Dig., 2016, pp. 1-2.

9. Vardi, X. Zhao, J. A. del Alamo, “Quantum-Size Effects in Sub 10-nm Fin Width InGaAs FinFETs”, in IEDM Tech. Dig., 2015, pp. 807-810.

10. T. P. Xiao, X. Zhao, S. Agarwal, E. Yablonovitch, “Impact of Interface Defects on Tunneling FET Turn-on Steepness”, 2015 4^th Berkeley Symposium on Energy Efficient Electronic Systems, Berkeley, CA, Oct, 2015.

11. J. A. del Alamo, D. A. Antoniadis, J. Lin, W. Lu, A. Vardi and X. Zhao, “III-V MOSFETs for future CMOS”, Invited Paper at IEEE Compound Semicoductor Symposium, New Orleans, LA, Oct, 2015.

12. X. Zhao, A. Vardy, J. A. del Alamo, “InGaAs/InAs Heterojunction Vertical Nanowire Tunnel FETs Fabricated by a Top-down Approach”, in IEDM Tech. Dig., 2014, pp. 590-593.

13. Vardi, X. Zhao and J. A. del Alamo, “InGaAs Double-Gate Fin-Sidewall MOSFET”, in Proc. 72nd Annu. Device Res. Conf., June. 2014, pp. 219-220.

14. X. Zhao, J. Lin, C. Heidelberger, E. A. Fitzgerald and J. A. del Alamo, “Vertical Nanowire InGaAs MOSFETs Fabricated by a Top-down Approach”, in IEDM Tech. Dig., 2013, pp. 695-698.

15. J. Lin, X. Zhao, T. Yu, D. A. Antoniadis, and J. A. del Alamo, “A New Self-aligned Quantum-Well MOSFET Architecture Fabricated by a Scalable Tight Pitch Process”, in IEDM Tech. Dig., 2013, pp. 757-760.

16. J. A. del Alamo, D. Antoniadis, A. Guo, D.-H. Kim, T.-W. Kim, J. Lin, W. Lu, A. Vardi, and X. Zhao, “InGaAs MOSFETs for CMOS: Recent Advances in Process Technology”, in IEDM Tech. Dig., 2013, pp. 24-27.

Conference presentations (Chronological order)

1. X. Zhao, A. Vardy, and J. A. del Alamo, “Modeling the Parasitic Bipolar Effect in InGaAs FinFETs”, Compound Semiconductor Week, Cambridge, US, May 29 – June 1, 2018.

2. W. Lu, X. Zhao, and J. A. del Alamo, “Towards Sub-10 nm Diameter III-V Vertical Nanowire Transistors”, TECHCON 2017, Austin, TX, Sep 11-13, 2017.

3. A. Vardi, J. Lin, W. Lu, X. Zhao and J. A. del Alamo, “A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs.” Plenary Session Invited Talk, CS MANTECH 2017, Indian Wells, CA, May 22-25, 2017.

4. X. Zhao, C. Heidelberger, E. A. Fitzgerald and J. A. del Alamo, “Source/Drain Asymmetry in InGaAs Vertical Nanowire MOSFETs”, TECHCON 2016, Austin, TX, Sep 11-13, 2016.